Not established: supply is constrained, but the extent is uncertain. Confidence: low.
TSMC confirms its most advanced chipmaking capacity is short of demand. Its CEO said in July: "the demand and the supply, the gap is so big, so we are working very hard to narrow the gap." But public evidence on waits, prices and whether new capacity will be enough is thin, so only one of our four signs is confirmed. That isn't enough to rate how severe the shortage is.
Outlook: TSMC raised 2026 capex to $60–64B, and says it does "not foresee any bottlenecks" to its capacity expansion plans. It expects strong demand "all the way to probably 2029, 2030."
New here? Skip to Background below for the basics. Coming back? Start with What changed.
This month
October 2026 · Updated Oct 4 · Next update after TSMC's Oct 15 call
What changed since last month
First reading. From next month this section leads with what moved and why.
Scorecard
Warning sign | What we saw | Reading | Source |
Long waits | Not confirmed. Reports that 3nm is booked into 2027 and 2nm into 2028 come from secondary analyses, not TSMC. | ⚪ Unknown | — |
Orders above supply | TSMC CEO C.C. Wei, on unconstrained demand for its most advanced chips: "the demand and the supply, the gap is so big, so we are working very hard to narrow the gap." He didn't split this between 3nm and 2nm. | 🔴 Yes | |
Prices going up | Not confirmed. Taiwanese press reports 3nm price increases of up to 15% in late 2026. TSMC hasn't confirmed this, and Wei said: "I don't want to squeeze them out from the market." | ⚪ Unknown | |
New capacity not enough | Not established with separate evidence. TSMC is building new fabs, converting 5nm tools to 3nm, and raising capex, and says it doesn't foresee bottlenecks to that expansion. No source we trust says this planned capacity will still fall short. | ⚪ Unknown |
Score: 1 red, 0 green, 0 mixed, 3 unknown = ⚪ Not established. Supply is confirmed constrained, but fewer than two signs are confirmed, so we can't rate how severe it is. Confidence is low. We don't reuse the CEO's "gap" comment for a second sign.
Dates to watch
Oct 8: TSMC September sales.
Oct 15: TSMC Q3 earnings call. Listen for confirmed pricing, 3nm and 2nm ramp progress, and how long advanced capacity stays short.
Oct 22 and Oct 29 (expected): Intel (Oct 22) and Samsung (Oct 29) results. Any confirmed new leading-edge foundry customers.
"Expected" dates come from earnings calendars. The company hasn't announced them yet.
Status history
- Oct 2026: ⚪ Not established (1 red, 3 unknown), low confidence. First reading.
Background
Reference. Updated when the facts change, not every month.
What it is
Chips are printed onto round silicon wafers. The newest processes, called 3nm and 2nm, pack the most transistors into the smallest space. That makes chips faster and more power-efficient. They are separate pools of capacity: different processes, at different stages of ramp, used by different chip designs. A chip designed for one can't simply move to the other.
Where it sits: Chip design (NVIDIA, AMD, Broadcom, Apple and others) → printed on 3nm/2nm wafers at TSMC → then packaged. AI accelerators are usually packaged with HBM memory using TSMC's CoWoS. Phone chips like Apple's use different packaging → device, or server and data center
TSMC makes most of the world's leading-edge chips. It held about 70% of the whole foundry market at the end of 2025 (TrendForce), and a larger share at the very top end.
When something is short, two things happen. The seller can charge more and stays fully booked. The buyer has orders it can't fill on time. Same shortage, opposite effect on the stock.
Why can't they just build more?
- A new fab costs tens of billions and takes years.
- The key machine has one maker. The most advanced printing tools (EUV machines) come only from ASML in the Netherlands. That's a structural concentration, not a current shortage: TSMC says it does "not foresee any bottlenecks to our capacity expansion plans."
- New processes cost more at first. TSMC says the 2nm ramp will dilute its gross margin by about 3–4 points. That reflects ramp costs like depreciation and utilization. It isn't evidence about yields.
- TSMC is spending heavily. It raised 2026 capex to $60–64B, from $52–56B, and expects the next three years' capex to be "even more significantly higher than the past three years."
How big is it, and how fast is it growing?
Measure | Number |
7nm and smaller, share of TSMC wafer revenue (Q2 2026) | 77% |
2nm share of wafer revenue (Q2 2026) | 3%, and ramping |
3nm monthly capacity (press reports) | About 130,000 wafers a month in early 2026, rising to about 160,000–175,000 in Q2. This is wafer capacity, not finished working chips. |
TSMC 2026 revenue growth guidance | Slightly above 40% in US dollars |
Where the capex goes
TSMC's split of its 2026 budget of $60–64B:
Bucket | Share | About |
Advanced processes (3nm, 2nm and newer) | 70–80% | $42–51B |
Specialty processes (older, specialized chips like power and sensors) | About 10% | About $6B |
Advanced packaging, testing, mask making and other | 10–20% | $6–13B |
- Why it rose: TSMC CEO C.C. Wei pointed to rising demand, and also said "we buy the tools with inflation price." So part of the increase is higher tool prices, not only more capacity.
- Where it's built: an extra $100B in Arizona for "probably additional four or more fabs" plus advanced packaging, and 13 leading-edge and advanced packaging fabs planned in Taiwan.
- Who gets paid: most of the money buys chipmaking tools, so the big equipment makers are the main beneficiaries. See the table below.
Who wins, who waits
The effects below are our interpretation, not company statements.
Company | Likely effect | Why |
Wins | Owns most leading-edge capacity. Gross margin was 67.7% in Q2 2026, and it guides 2026 revenue growth slightly above 40%. | |
ASML (ASML) | Wins | Sole maker of the EUV machines every new leading-edge line needs. Taiwan rose to 30% of its Q2 2026 sales from 23% in Q1, and it raised 2026 guidance to €43–45B. |
KLA (KLAC) | Wins | Makes inspection and measurement tools that catch defects, needed more with every new process and packaging step. Taiwan was 31% of its June-quarter sales, its largest region. It expects 2026 advanced packaging revenue of about $1.1B, up more than 70%. |
Lam Research (LRCX) | Wins | Makes etch and deposition tools, which carve patterns and lay down thin films. Taiwan was 27% of June-quarter sales, its largest region, and it guided next-quarter revenue to $8.1B from $6.72B. China (26% of sales) and memory chips also drive its results, so it isn't a pure TSMC play. |
Applied Materials (AMAT) | Wins | The broadest range of chipmaking tools, plus packaging tools. Taiwan was 27% of its sales. It expects 2026 equipment sales to grow more than 30% and packaging sales more than 50%. Memory chips are also a big driver. |
Samsung Foundry, Intel (INTC) | Maybe | Possible alternatives if TSMC stays full. Winning a customer doesn't immediately free capacity: a chip has to be redesigned and qualified for a new foundry, and performance and cost have to work. Customer wins here are mostly reported, not confirmed. |
Mixed | One of TSMC's largest customers, so likely well placed in the queue. Higher wafer prices would raise its costs. | |
Exposed | Their AI and custom chips use the same advanced lines, and any price increase raises their costs. | |
Apple, Qualcomm, MediaTek | Exposed | Phone chips compete with AI chips for TSMC's newest processes. |
The takeaway: TSMC confirms constrained advanced-node supply, but public evidence can't yet measure how severe it is or how long it lasts.
When does it end, and what could replace it?
- 2026 onward: TSMC converts 5nm tools to 3nm in Taiwan and ramps 2nm. New Arizona fabs, including 2nm, add capacity over time.
- Backup suppliers: Samsung and Intel are competing for TSMC's customers, but switching takes redesign and qualification.
- TSMC's view: demand strong "all the way to probably 2029, 2030," though Wei added: "Whether in between there's a dip or not, I'm not very sure."
What could go wrong for this view
- Capacity catches up. Heavy capex, tool conversions and no foreseen equipment bottlenecks could close the gap faster than expected.
- Demand dips. TSMC's own CEO isn't sure there won't be a dip before 2029–2030.
How to read a change
Good easing
Bookings shorten because new 2nm lines came online, while TSMC keeps raising guidance. More chips get made and costs stop climbing.
Bad easing
Bookings shorten because customers pushed out orders. TSMC would talk about inventory or cut capex, a warning for the whole AI chain.
What would change our view
- Turns tight: TSMC confirms price increases, publishes lead-time or booking data, or says advanced capacity stays short even after planned additions. Each would add a confirmed red sign.
- Gets easier (good): 2nm ramps on schedule and Samsung or Intel win big confirmed leading-edge customers.
- Gets easier (bad): TSMC trims capex or warns about AI customers' inventory.
Past scorecards
Each month the previous scorecard moves here, newest first.
- None yet. October 2026 is the first reading.
Evidence and sources
Company statements
- TSMC Q2 2026 call (Jul 16, 2026): Wei, "the demand and the supply, the gap is so big, so we are working very hard to narrow the gap"; "I don't want to squeeze them out from the market"; "we continue to convert 5-nanometer tools to support 3-nanometer capacity in Taiwan"; "We do not foresee any bottlenecks to our capacity expansion plans"; capex $60–64B; capex in the next three years "even more significantly higher than the past three years"; 2026 growth "slightly above 40%"; 2nm 3% and 7nm-and-below 77% of wafer revenue; 2nm ramp dilutes gross margin about 3–4 points; demand strong "to probably 2029, 2030." No explicit comparison of 3nm and 2nm tightness. Transcript · Investing.com transcript
- TSMC Q2 2026 call (Jul 16, 2026): "about 70% to 80% of the 2026 capital budget will be allocated for advanced process technologies, about 10% will be spent for specialty technologies, and about 10% to 20% will be spent for advanced packaging, testing, mask making and others"; "we buy the tools with inflation price"; additional $100B in Arizona, "probably additional four or more fabs"; 13 leading-edge and advanced packaging fabs in Taiwan. Transcript
- ASML Q2 2026 (Jul 15, 2026): Taiwan 30% of sales, up from 23% in Q1; 2026 guidance €43–45B. TrendForce
- KLA Q4 fiscal 2026 (Jul 2026): Taiwan 31% of revenue; advanced packaging process control revenue about $1.1B in 2026, up more than 70%. Shareholder letter
- Lam Research June 2026 quarter (Jul 29, 2026): revenue $6.72B; Taiwan 27%, China 26%; next-quarter guidance $8.10B. Release
- Applied Materials Q2 fiscal 2026 (May 2026): Taiwan 27% of sales; 2026 equipment growth over 30%, packaging over 50%. TrendForce
Press reports (not scored)
- 3nm price increases of up to 15% in 2H26 and 5–10% in 2027; monthly 3nm capacity 130k to 160–175k wafers; TSMC 70.4% foundry share in 4Q25 (TrendForce data). Original reports from Commercial Times, Liberty Times and UDN. TrendForce News, May 27
- Dates: TSMC financial calendar
- Where sources disagree: many analysts describe TSMC's leading edge as sold out for years, but TSMC hasn't published booking or lead-time data. Some argue packaging, not wafers, is the tighter constraint in 2026.
Words used on this page
- nm (nanometer): a label for each new chipmaking process. Smaller numbers mean newer, denser chips.
- Node / process: a generation of chipmaking technology, like 3nm or 2nm.
- Foundry: a company that makes chips designed by others, like TSMC.
- Wafer: the round silicon disc chips are printed on. Wafer capacity isn't the same as finished working chips.
- EUV (Extreme Ultraviolet) lithography: the machine that prints the finest chip patterns. Only ASML makes it.
- Qualification: testing that a chip made at a new foundry or process meets the customer's requirements.
- Gross margin dilution: a temporary drop in profit margin while a new process ramps up.
- Capex (capital expenditure): money spent on factories and equipment.
- Etch / deposition: chipmaking steps that carve patterns into the wafer and lay down thin layers of material.
- Process control: inspection and measurement tools that find defects during chipmaking.
- Mask: the stencil used to print a chip's pattern onto the wafer.
- Specialty process: an older, specialized chipmaking process for chips like power, sensors or radio.
- CoWoS: TSMC's advanced packaging used for most AI accelerators. See the CoWoS page.
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